Two-dimensional (2D) layered transition metal chalcogenides (LTMC) have been emerging as new materials for electronic applications. For instance, two-dimensional MoS2 layers are currently developed for use in fields including field effect transistors, low power switches, optoelectronics, and spintronics.
MoS2 presents itself as a stack of molecular layers held together by weak van der Waals interactions. LTMC materials in general and MoS2 in particular can be separated by exfoliation/delamination techniques into individual two-dimensional sheets. Due to their intrinsic two-dimensional character, these materials show remarkable optical and electronic properties and, importantly, offer a concrete prospect for scaling semiconductor devices to the atomic scale.
In 2011, B. Radisavljevic et al (Nat. Nanotech. 6, 147 (2011)) have integrated for the first time a micrometric MoS2 flake, obtained by mechanical exfoliation from a natural bulk crystal, as a channel layer in a double gated field effect transistor therein showing outstanding performances which make MoS2 competitive with ultra-thin silicon channels.
Large area MoS2 layers have recently been grown by various teams (Arend M. van der Zande et al. Nature Materials 12,554-561(2013); Keng-Ku Liu et al. Nano Lett., 12 (3), 1538 (2012); Masihhur R. Laskar et al. Appl. Phys. Lett. 102, 252108 (2013)), which paves the way to the forthcoming development of manufacturing technology.
Some challenges remain however to be met. One of these is the difficulty to obtain large high quality MoS2 films. High quality MoS2 (in term of surface roughness) has been grown on Si substrates but many applications require the MoS2 film to be present on a dielectric substrate. For instance, a semiconductor substrate such as Si is not suitable for electrical measurements because it induces current leakage.
The synthesis of high quality MoS2 directly on top of dielectric materials is a challenging research topic. The main issue is related to the extremely high temperatures (>700° C.) involved in synthesis processes. These temperatures are not compatible with wafer processing in a standard pilot line environment.
A promising route is the transfer of MoS2 layers from a template substrate to a dielectric substrate. This process is however prone to contamination and degradation issues.